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JANSR2N7395
Formerly FSL130R4
June 1998
8A, 100V, 0.230 Ohm, Rad Hard, N-Channel Power MOSFET
Description
The Discrete Products Operation of Intersil Corporation has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Also available at other radiation and screening levels. See us on the web, Intersil's home page: http://www.intersil.com. Contact your local Intersil Sales Office for additional information.
Features
* 8A, 100V, rDS(ON) = 0.230 * Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) * Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias * Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM * Photo Current - 1.5nA Per-RAD(Si)/s Typically * Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2
Ordering Information
PART NUMBER JANSR2N7395 PACKAGE TO-205AF BRAND JANSR2N7395
Symbol
Die Family TA17636. MIL-PRF-19500/631.
Package
TO-205AF
D
G
S
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4371.1
2-28
JANSR2N7395
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified JANSR2N7395 100 100 8 5 24 20 25 10 0.20 24 8 24 -55 to 150 300 1.0 UNITS V V A A A V W W W/oC A A A oC oC g
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100H, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA TC = -55oC TC = 25oC TC = 125oC MIN 100 1.5 0.5 VGS = 0V to 20V VGS = 0V to 12V VGS = 0V to 2V VDD = 50V, ID = 8A, TYP 0.170 33 6.5 17 MAX 5.0 4.0 25 250 100 200 1.93 0.230 0.361 70 220 100 90 64 43 2.4 8.7 22 5.0 175 UNITS V V V V A A nA nA V ns ns ns ns nC nC nC nC nC
oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage
Zero Gate Voltage Drain Current
IDSS
VDS = 80V, VGS = 0V VGS = 20V
TC = 25oC TC = 125oC TC = 25oC TC = 125oC
Gate to Source Leakage Current
IGSS
Drain to Source On-State Voltage Drain to Source On Resistance
VDS(ON) rDS(ON)12
VGS = 12V, ID = 8A ID = 5A, VGS = 12V TC = 25oC TC = 125oC
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Not on Slash Sheet) Gate Charge at 12V Threshold Gate Charg (Not on Slash Sheet) Gate Charge Source Gate Charge Drain Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
td(ON) tr td(OFF) tf Qg(TOT) Qg(12) Qg(TH) Qgs Qgd RJC RJA
VDD = 50V, ID = 8A, RL = 6.25, VGS = 12V, RGS = 7.5
2-29
JANSR2N7395
Source to Drain Diode Specifications
PARAMETER Forward Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 8A ISD = 8A, dISD/dt = 100A/s MIN 0.6 TYP MAX 1.8 330 UNITS V ns
Electrical Specifications up to 100K RAD
PARAMETER Drain to Source Breakdown Volts Gate to Source Threshold Volts Gate to Body Leakage Zero Gate Leakage Drain to Source On-State Volts Drain to Source On Resistance NOTES: 1. Pulse test, 300s Max. 2. Absolute value. (Note 3) (Note 3) (Notes 2, 3) (Note 3) (Notes 1, 3) (Notes 1, 3)
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IGSS IDSS VDS(ON) rDS(ON)12 TEST CONDITIONS VGS = 0, ID = 1mA VGS = VDS, ID = 1mA VGS = 20V, VDS = 0V VGS = 0, VDS = 80V VGS = 12V, ID = 8A VGS = 12V, ID = 5A MIN 100 1.5 MAX 4.0 100 25 1.93 0.230 UNITS V V nA A V
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS .
Single Event Effects (SEB, SEGR) (Note 4)
ENVIRONMENT (NOTE 5) ION SPECIES Ni Br Br Br NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). TYPICAL LET (MeV/mg/cm) 26 37 37 37 TYPICAL RANGE () 43 36 36 36 APPLIED VGS BIAS (V) -20 -10 -15 -20 (NOTE 6) MAXIMUM VDS BIAS (V) 100 100 80 50
TEST Single Event Effects Safe Operating Area
SYMBOL SEESOA
Typical Performance Curves
Unless Otherwise Specified
LET = 26MeV/mg/cm2, RANGE = 43 LET = 37MeV/mg/cm2, RANGE = 36 120 100 80 VDS (V) 60 40 20 0 0 TEMP = 25oC -5 -10 VGS (V) -15 -20 -25 FLUENCE = 1E5 IONS/cm2 (TYPICAL) LIMITING INDUCTANCE (HENRY)
1E-3
1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6
1E-7 10
30
100 DRAIN SUPPLY (V)
300
1000
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS
2-30
JANSR2N7395 Typical Performance Curves
10
Unless Otherwise Specified
(Continued)
100 TC = 25oC ID , DRAIN CURRENT (A)
8 ID , DRAIN (A)
10
100s
6
1ms 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
4
1
2
100ms
0 -50
0
50
100
150
100
TC , CASE TEMPERATURE (oC)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5 PULSE DURATION = 250ms, VGS = 12V, ID = 5A NORMALIZED rDS(ON) 2.0
12V
QG
1.5
QGS VG
QGD
1.0
0.5
0.0 -80 CHARGE
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 5. BASIC GATE CHARGE WAVEFORM
FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
NORMALIZED THERMAL RESPONSE (ZJC)
10
1 0.5 0.2 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 0.001 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 PDM t1
0.1
t2 101
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-31
JANSR2N7395 Typical Performance Curves
100 IAS , AVALANCHE CURRENT (A)
Unless Otherwise Specified
(Continued)
STARTING TJ = 25oC 10 STARTING TJ = 150oC IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.1 1 tAV , TIME IN AVALANCHE (ms) 10
1 0.01
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L + CURRENT I TRANSFORMER AS BVDSS tP IAS + VDD VDS VDD
-
VARY tP TO OBTAIN REQUIRED PEAK IAS VGS 20V
50
DUT 50V-150V 50 tAV
0V
tP
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
VDD
tON td(ON)
tOFF td(OFF) tr tf 90%
RL VDS VGS = 12V DUT 0V RGS
VDS
90%
10%
10%
90% VGS 10% 50% PULSE WIDTH 50%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
2-32
JANSR2N7395 Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified
PARAMETER Gate to Source Leakage Current Zero Gate Voltage Drain Current Drain to Source On Resistance Gate Threshold Voltage NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. SYMBOL IGSS IDSS rDS(ON) VGS(TH) TEST CONDITIONS VGS = 20V VDS = 80% Rated Value TC = 25oC at Rated ID ID = 1.0mA MAX 20 (Note 7) 25 (Note 7) 20% (Note 8) 20% (Note 8) UNITS nA A V
Screening Information
TEST Gate Stress Pind Pre Burn-In Tests (Note 9) VGS = 30V, t = 250s Required MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours 5% MIL-S-19500, Group A, Subgroups 2 and 3 JANS
Steady State Gate Bias (Gate Stress)
Interim Electrical Tests (Note 9) Steady State Reverse Bias (Drain Stress)
PDA Final Electrical Tests (Note 9)
NOTE: 9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance SYMBOL SOA IAS VSD VSD TEST CONDITIONS VDS = 80V, t = 10ms VGS(PEAK) = 15V, L = 0.1mH tH = 10ms; VH = 25V; IH = 2A tH = 500ms; VH = 25V; IH = 1A MAX 1.5 24 125 250 UNITS A A mV mV
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JANSR2N7395 Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning Attributes Data Sheet Hi-Rel Lot Traveler HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A G. Group B H. Group C I. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data
G. Group B
H. Group C
I. Group D
2-34
JANSR2N7395 TO-205AF
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE
OD OD1 A P
INCHES SYMBOL A Ob MIN 0.160 0.016 0.350 0.315 0.095 0.190 0.095 0.010 0.028 0.029 0.500 0.075 MAX 0.180 0.021 0.370 0.335 0.105 0.210 0.105 0.020 0.034 0.045 0.560 -
MILLIMETERS MIN 4.07 0.41 8.89 8.01 2.42 4.83 2.42 0.26 0.72 0.74 12.70 1.91 MAX 4.57 0.53 9.39 8.50 2.66 5.33 2.66 0.50 0.86 1.14 14.22 NOTES 2, 3 4 4 4 3 5
h
L
SEATING PLANE Ob
OD OD1 e e1
e e1
2 90o 3
e2 h j k L P k
e2
45o
1
j
NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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